SMMU_CB11_PMCNTENCLR (FPD_SMMU_TCU) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID: AM012
Release Date: 2023-08-29
Revision: 1.3

SMMU_CB11_PMCNTENCLR (FPD_SMMU_TCU) Register Description

Register Name	SMMU_CB11_PMCNTENCLR
Relative Address	0x000002BF44
Absolute Address	0x00FD82BF44 (FPD_SMMU_TCU)
Width	32
Type	woWrite-only
Reset Value	0x00000000
Description	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.

SMMU_CB11_PMCNTENCLR (FPD_SMMU_TCU) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
P3	3	woWrite-only	0x0	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
P2	2	woWrite-only	0x0	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
P1	1	woWrite-only	0x0	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
P0	0	woWrite-only	0x0	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.