PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 (CPM4_PCIE1_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)
Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 (CPM4_PCIE1_ATTR) Register Description

Register NamePF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3
Relative Address0x00000005A0
Absolute Address 0x00FCA605A0 (CPM4_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionSets the exit latency from L0s state to be applied (at 8G) where separate clocks are used.
Transferred to the Link Capabilities register.

This register should only be written to during reset of the PCIe block

PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 (CPM4_PCIE1_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 2:0rwNormal read/write0x0Sets the exit latency from L0s state to be applied (at 8G) where separate clocks are used.
Transferred to the Link Capabilities register.