PF0_DEV_CONTROL2_PERMIT_IDO_REQ_EN (CPM5_PCIE_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)
Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PF0_DEV_CONTROL2_PERMIT_IDO_REQ_EN (CPM5_PCIE_ATTR) Register Description

Register NamePF0_DEV_CONTROL2_PERMIT_IDO_REQ_EN
Relative Address0x0000000E60
Absolute Address 0x00FCE08E60 (CPM5_PCIE0_ATTR)
0x00FCE88E60 (CPM5_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPermit IDO Requester Enable: Permit IO Req by making Device Control2 IO Reqester Enable bit RW (HW does not support IDO)

This register should only be written to during reset of the PCIe block

PF0_DEV_CONTROL2_PERMIT_IDO_REQ_EN (CPM5_PCIE_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 0rwNormal read/write0x0Permit IDO Requester Enable: Permit IO Req by making Device Control2 IO Reqester Enable bit RW (HW does not support IDO)