agent_iccc0_llc_event_counter_mask_1 (CPM4_L2_CSR) Register Description
| Register Name | agent_iccc0_llc_event_counter_mask_1 |
|---|
| Relative Address | 0x0000006198 |
|---|
| Absolute Address |
0x00FCD06198 (CPM4_L2_CSR)
|
|---|
| Width | 64 |
|---|
| Type | mixedMixed types. See bit-field details. |
|---|
| Reset Value | 0x00000000 |
|---|
| Description | This register is used to program its corresponding event counter. |
|---|
This register is used to program its corresponding event counter. Each bit of this register enables the performance counter to increment if the event occurs. A value of 1 for a bit indicates that this event should be counted. If multiple bits are set to 1, the logic will only count if all of the corresponding events occur on the same cycle. This allows for combinations of events, such as a cache miss that causes an eviction. The events that can be counted are all related to cache accesses and occur in the same cycle of the pipeline, so they can be combined easily. When an event satisfies all of the requirements, the llc_event_counter_1 register will be updated. A value of 1 indicates that the event is selected for counting. A value of 0 the event is not selected. By default, this register will be set to 0 for all bits, indicating no event counting should occur.
agent_iccc0_llc_event_counter_mask_1 (CPM4_L2_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| UNSD_63_28 | 63:28 | roRead-only | 0x0 | |
| e27 | 27 | rwNormal read/write | 0x0 | Allocate conflict |
| e26 | 26 | rwNormal read/write | 0x0 | Indx after indx tmp conflict |
| e25 | 25 | rwNormal read/write | 0x0 | Wr after alloc conflict |
| e24 | 24 | rwNormal read/write | 0x0 | Wr after evict conflict |
| e23 | 23 | rwNormal read/write | 0x0 | Rd after rd alloc conflict |
| e22 | 22 | rwNormal read/write | 0x0 | Rd alloc after wr conflict |
| e21 | 21 | rwNormal read/write | 0x0 | Rd after evict |
| e20 | 20 | rwNormal read/write | 0x0 | Tag update |
| e19 | 19 | rwNormal read/write | 0x0 | Request CleanUnique |
| e18 | 18 | rwNormal read/write | 0x0 | External snoop |
| e17 | 17 | rwNormal read/write | 0x0 | Excl wr fails store conditional |
| e16 | 16 | rwNormal read/write | 0x0 | Exclusive write |
| e15 | 15 | rwNormal read/write | 0x0 | Atomic op |
| e14 | 14 | rwNormal read/write | 0x0 | Write through |
| e13 | 13 | rwNormal read/write | 0x0 | Rd dealloc on dirty |
| e12 | 12 | rwNormal read/write | 0x0 | Rd dealloc |
| e11 | 11 | rwNormal read/write | 0x0 | Partial line wr |
| e10 | 10 | rwNormal read/write | 0x0 | Fetch due to partial wr |
| e9 | 9 | rwNormal read/write | 0x0 | Retry access |
| e8 | 8 | rwNormal read/write | 0x0 | Retry needed |
| e7 | 7 | rwNormal read/write | 0x0 | Eviction |
| e6 | 6 | rwNormal read/write | 0x0 | Cache maint op |
| e5 | 5 | rwNormal read/write | 0x0 | Partial write |
| e4 | 4 | rwNormal read/write | 0x0 | Cache miss |
| e3 | 3 | rwNormal read/write | 0x0 | Cache hit |
| e2 | 2 | rwNormal read/write | 0x0 | Scratchpad access |
| e1 | 1 | rwNormal read/write | 0x0 | Cache write |
| e0 | 0 | rwNormal read/write | 0x0 | Cache read |