CPI1_RXREQ_ERROR_STAT (CPM4_SLCR) Register Description
| Register Name | CPI1_RXREQ_ERROR_STAT |
|---|---|
| Relative Address | 0x00000003E0 |
| Absolute Address | 0x00FCA103E0 (CPM4_SLCR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Error Status Register for errors detected in CPI 1 RXREQ bridge. This is a sticky register that holds the value of the error until cleared by a value of 1. |
CPI1_RXREQ_ERROR_STAT (CPM4_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:6 | roRead-only | 0x0 | Reserved |
| skid_fifo_of | 4 | wtcReadable, write a 1 to clear | 0x0 | Status of skid fifo overflow error |
| flit_fifo_of | 2 | wtcReadable, write a 1 to clear | 0x0 | Status of flit fifo overflow error |
| out_cred_cntr_of | 1 | wtcReadable, write a 1 to clear | 0x0 | Status of output credit counter overflow error |
| in_cred_cntr_of | 0 | wtcReadable, write a 1 to clear | 0x0 | Status of input credit counter overflow error |