AXISTEN_IF_ENABLE_CLIENT_TAG (CPM4_PCIE1_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

AXISTEN_IF_ENABLE_CLIENT_TAG (CPM4_PCIE1_ATTR) Register Description

Register NameAXISTEN_IF_ENABLE_CLIENT_TAG
Relative Address0x0000000074
Absolute Address 0x00FCA60074 (CPM4_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAXI Streaming Enhanced Inteface Tag management option for RQ interface: When this attribute is FALSE, Tag management for Non-Posted transactions initiated from the requester request interface is performed by the PCIe Hard Block. That is, for each Non-Posted request, the core allocates the Tag for the transaction and communicates it to the client.When this attribute set to TRUE,
internal tag management is disabled, allowing the user to supply the tag to be used for each request. The user must present the Tag field in the Request descriptor header in the range 0-31 when attribute PF0_DEV_CAP_EXT_TAG_SUPPORTED is FALSE, while Tag field must be in the range 0-255 when attribute PF0_DEV_CAP_EXT_TAG_SUPPORTED is TRUE. When this attribute is TURE and attribute PF0_DEV_CAP_EXT_TAG_SUPPORTED is TRUE, attribute AXISTEN_IF_ENABLE_256_TAGS should be set to TRUE.

This register should only be written to during reset of the PCIe block

AXISTEN_IF_ENABLE_CLIENT_TAG (CPM4_PCIE1_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 0rwNormal read/write0x0AXI Streaming Enhanced Inteface Tag management option for RQ interface: When this attribute is FALSE, Tag management for Non-Posted transactions initiated from the requester request interface is performed by the PCIe Hard Block. That is, for each Non-Posted request, the core allocates the Tag for the transaction and communicates it to the client.When this attribute set to TRUE,
internal tag management is disabled, allowing the user to supply the tag to be used for each request. The user must present the Tag field in the Request descriptor header in the range 0-31 when attribute PF0_DEV_CAP_EXT_TAG_SUPPORTED is FALSE, while Tag field must be in the range 0-255 when attribute PF0_DEV_CAP_EXT_TAG_SUPPORTED is TRUE. When this attribute is TURE and attribute PF0_DEV_CAP_EXT_TAG_SUPPORTED is TRUE, attribute AXISTEN_IF_ENABLE_256_TAGS should be set to TRUE.