PL_UNCORR_IR_ENABLE (CPM5_SLCR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PL_UNCORR_IR_ENABLE (CPM5_SLCR) Register Description

Register NamePL_UNCORR_IR_ENABLE
Relative Address0x0000000388
Absolute Address 0x00FCDD0388 (CPM5_SLCR)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionInterrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)

PL_UNCORR_IR_ENABLE (CPM5_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
npi3_error_interrupt25woWrite-only0x0Enable for NPI GT Quad 3 error interrupt.
npi2_error_interrupt24woWrite-only0x0Enable for NPI GT Quad 2 error interrupt.
npi1_error_interrupt23woWrite-only0x0Enable for NPI GT Quad 1 error interrupt.
npi0_error_interrupt22woWrite-only0x0Enable for NPI GT Quad 0 error interrupt.
cxs1_error_interrupt21woWrite-only0x0Enable for cxs1 upsizer error interrupt.
cxs0_error_interrupt20woWrite-only0x0Enable for cxs0 upsizer error interrupt.
cpipe_err19woWrite-only0x0Enable for interrupt from CPIPE
crx_pll_lock18woWrite-only0x0Enable for PLL lock from CRX
intcpm_isr17woWrite-only0x0Enable for Latent/mission/dataparity and timeout interrupt from Interconnect
pl_irq116woWrite-only0x0Enable for interrupt 1 from PL
pl_irq015woWrite-only0x0Enable for interrupt 0 from PL
cpi1_err14woWrite-only0x0Enable for error interrupt from CPI 1
cpi0_err13woWrite-only0x0Enable for error interrupt from CPI 0
addrremap_err12woWrite-only0x0Enable for addresss translation error interrupt from addrremap block
l2_cache1_uncorr_err11woWrite-only0x0Enable for uncorrectable error from L2 cache 1
l2_cache1_corr_err10woWrite-only0x0Enable for correctable error from L2 cache 1
l2_cache0_uncorr_err 9woWrite-only0x0Enable for uncorrectable error from L2 cache 0
l2_cache0_corr_err 8woWrite-only0x0Enable for correctable error from L2 cache 0
cmn_pmu_event 7woWrite-only0x0Enable for performance counter overflow interrupt from CMN
cmn_faults 6woWrite-only0x0Enable for secure fault interrupt from CMN
cmn_faultns 5woWrite-only0x0Enable for non-secure fault interrupt from CMN
cmn_errs 4woWrite-only0x0Enable for secure error interrupt from CMN
cmn_errns 3woWrite-only0x0Enable for non-secure error interrupt from CMN
pcie1_err 2woWrite-only0x0Enable for pcie1 interrupt events and errors
pcie0_err 1woWrite-only0x0Enable for pcie0 interrupt events and errors
apb_err 0woWrite-only0x0Enable for an APB error interrupt.