GICP_PMC_ISR (PMC_GLOBAL) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

GICP_PMC_ISR (PMC_GLOBAL) Register Description

Register NameGICP_PMC_ISR
Relative Address0x00000300A0
Absolute Address 0x00F11400A0 (PMC_GLOBAL)
Width32
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionPMC GICP Aggregate Interrupt Status

Alternate register name: GICP_PMC_IRQ_STATUS

GICP_PMC_ISR (PMC_GLOBAL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
src4 4wtcReadable, write a 1 to clear0x0Create single interrupt source for PMC from GICP4
src3 3wtcReadable, write a 1 to clear0x0Create single interrupt source for PMC from GICP3
src2 2wtcReadable, write a 1 to clear0x0Create single interrupt source for PMC from GICP2
src1 1wtcReadable, write a 1 to clear0x0Create single interrupt source for PMC from GICP1
src0 0wtcReadable, write a 1 to clear0x0Create single interrupt source for PMC from GICP0