PSM_Route (PSM_INT_CSR) Register Description
| Register Name | PSM_Route |
|---|---|
| Relative Address | 0x0000000020 |
| Absolute Address | 0x00FFC9E020 (PSM_INT_CSR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | PSM CPU Transaction Routing to NoC via FPD |
Alternate register name: psmublaze
PSM_Route (PSM_INT_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:1 | rwNormal read/write | 0x0 | 0: transactions will not get diverted to FPD 1: transactions through to FPD Note: Setting this bit allows for APU L2 cache coherency and SMMU address translation via TBU 0 |
| routing | 0 | rwNormal read/write | 0x0 | 0: transactions will not get diverted to FPD 1: transactions through to FPD Note: Setting this bit allows for APU L2 cache coherency and SMMU address translation via TBU 0 |