PMINTENSET_EL1 (DBG_A721_PMU) Register Description
| Register Name | PMINTENSET_EL1 |
|---|---|
| Relative Address | 0x0000000C40 |
| Absolute Address | 0x00F0D60C40 (DBG_APU1_PMU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Performance Monitors Interrupt Enable Set Register |
PMINTENSET_EL1 (DBG_A721_PMU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| C | 31 | rwNormal read/write | 0x0 | PMCCNTR_EL0 overflow interrupt request enable bit. |
| P | 5:0 | rwNormal read/write | 0x0 | Event counter overflow interrupt request enable bits for PMEVCNTR5_EL0 through PMEVCNTR0_EL0 respectively. |