C2H0_CHANNEL_PERFORMANCE_DATA_COUNT0 (CPM4_XDMA_CSR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

C2H0_CHANNEL_PERFORMANCE_DATA_COUNT0 (CPM4_XDMA_CSR) Register Description

Register NameC2H0_CHANNEL_PERFORMANCE_DATA_COUNT0
Relative Address0x00000010CC
Absolute Address 0x00E10010CC (CPM4_XDMA_CSR)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionC2H0_CHANNEL_PERFORMANCE_DATA_COUNT0

C2H0_CHANNEL_PERFORMANCE_DATA_COUNT0 (CPM4_XDMA_CSR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
pmon_dat_count31:0roRead-only0x0pmon_dat_count[31:0]. Increments for each valid read data beat while running. See PerformanceControl.Clear and PerformanceControl.Auto for clearing.