Config (PMC_EFUSE_CTRL) Register Description
| Register Name | Config |
|---|---|
| Relative Address | 0x0000000004 |
| Absolute Address | 0x00F1240004 (PMC_EFUSE_CTRL) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Configuration. Reset by POR only. |
Alternate register name: cfg
Config (PMC_EFUSE_CTRL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| APB_ErrorEn | 5 | rwNormal read/write | 0x0 | Enable the APB error signal to assert when the register module detects an address decode or other error on the APB programming interface: 0: no error signaling (APB_Err is kept low) 1: assert the APB_Err signal when an access error is detected Note: When an APB error occurs, the interrupt status bit in the ISR will be set regardless of this enable bit setting. Note: Field name reference: slverr_enable |
| Reserved | 3 | rwNormal read/write | 0x0 | reserved |
| margin_rd | 2 | rwNormal read/write | 0x0 | eFuse read margin control 0: Normal Read 1: Margin Read |
| pgm_en | 1 | rwNormal read/write | 0x0 | eFuse programming enable 0: Disabled programming 1: Enabled programming |
| Reserved | 0 | rwNormal read/write | 0x0 | reserved |