CTIOUTEN6 (DBG_A721_CTI) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

CTIOUTEN6 (DBG_A721_CTI) Register Description

Register NameCTIOUTEN6
Relative Address0x00000000B8
Absolute Address 0x00F0D500B8 (DBG_APU1_CTI)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionCTI Channel to Trigger 6 Enable Register

CTIOUTEN6 (DBG_A721_CTI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TRIGOUTEN 3:0rwNormal read/write0x0Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[6] output. There is one bit of the field for each of the four channels.When a 1 is written to a bit in this register, the channel input (ctichin) from the CTM is routed to the ctitrigout output. For example, enabling bit 0 enables ctichin[0] to cause a trigger event on the ctitrigout[6] output. When a 0 is written to any of the bits in this register, the channel input (ctichin) from the CTM is not routed to the ctitrigout output.Reading this register returns the programmed value.