agent_iccc0_ccc_indirect_ram_cont_4 (CPM5_L2_CFG) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

agent_iccc0_ccc_indirect_ram_cont_4 (CPM5_L2_CFG) Register Description

Register Nameagent_iccc0_ccc_indirect_ram_cont_4
Relative Address0x00000040B0
Absolute Address 0x00FCC040B0 (CPM5_L20_CSR)
0x00FCC840B0 (CPM5_L21_CSR)
Width64
TyperoRead-only
Reset Value0x00000000
DescriptionThis is the indirect access RAM content register.
Its use is conjunction with the indirect access trigger register.

This is the indirect access RAM content register. Its use is conjunction with the indirect access trigger register. On an indirect read, data is written to this register. On an indirect write, content from this register is written into the RAM. On a read-modify-write, content from this register is used for the XOR function. Since the RAM data width may be larger than 64 bits, multiple registers are used to hold the data. Any bits beyond the data width are unused. This register requires secure access, since it can modify directory content, causing incoherency for secure data.

agent_iccc0_ccc_indirect_ram_cont_4 (CPM5_L2_CFG) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
RAM_CONTENTS_319_25663:0roRead-only0x0