PL_LINK_CAP_MAX_LINK_SPEED (CPM5_PCIE_ATTR) Register Description
| Register Name | PL_LINK_CAP_MAX_LINK_SPEED |
|---|---|
| Relative Address | 0x00000000E4 |
| Absolute Address |
0x00FCE080E4 (CPM5_PCIE0_ATTR) 0x00FCE880E4 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Maximum Link Speed. Valid settings are: 00001b = Gen1, 00010b = Gen2, 00100b = Gen3, 01000b = Gen4, 10000b = Gen5. All other encodings are reserved. This setting is propagated to all layers in the design. |
This register should only be written to during reset of the PCIe block
PL_LINK_CAP_MAX_LINK_SPEED (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 4:0 | rwNormal read/write | 0x0 | Maximum Link Speed. Valid settings are: 00001b = Gen1, 00010b = Gen2, 00100b = Gen3, 01000b = Gen4, 10000b = Gen5. All other encodings are reserved. This setting is propagated to all layers in the design. |