SMMU_CB1_PMEVCNTR2 (FPD_SMMU_TCU) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

SMMU_CB1_PMEVCNTR2 (FPD_SMMU_TCU) Register Description

Register NameSMMU_CB1_PMEVCNTR2
Relative Address0x0000021E08
Absolute Address 0x00FD821E08 (FPD_SMMU_TCU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionProvides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.

SMMU_CB1_PMEVCNTR2 (FPD_SMMU_TCU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
bits31:0rwNormal read/write0x0Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.