MIO_Bank1_Slew_Sel (PMC_IOP_SLCR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

MIO_Bank1_Slew_Sel (PMC_IOP_SLCR) Register Description

Register NameMIO_Bank1_Slew_Sel
Relative Address0x0000000320
Absolute Address 0x00F1060320 (PMC_IOP_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionMIO_Bank1_Slew_Sel

Bit 0: PMC MIO pin 26. Bit 1: PMC MIO pin 27. etc. Bit 25: PMC MIO pin 51. Alternate register name: bnk1_sel_slew

MIO_Bank1_Slew_Sel (PMC_IOP_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:26razRead as zero0x0reserved
pins_26_5125:0rwNormal read/write0x0bit 0 corresponds to MIO_PIN_26 and bit 1 to MIO_PIN_27 so on
Slew rate control for IO.
0: Slow-slew
1: Fast-slew
Note: Field name reference: bnk1_sel_slew