LL_DISABLE_SCHED_TX_NAK (CPM5_PCIE_ATTR) Register Description
| Register Name | LL_DISABLE_SCHED_TX_NAK |
|---|---|
| Relative Address | 0x0000000504 |
| Absolute Address |
0x00FCE08504 (CPM5_PCIE0_ATTR) 0x00FCE88504 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Disable Scheduling on NAK: When TRUE, all actions related to NAK generation will be performed, except for NAK scehduled for transmission. When FALSE, for spec compliant behavior. |
This register should only be written to during reset of the PCIe block
LL_DISABLE_SCHED_TX_NAK (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 0 | rwNormal read/write | 0x0 | Disable Scheduling on NAK: When TRUE, all actions related to NAK generation will be performed, except for NAK scehduled for transmission. When FALSE, for spec compliant behavior. |