LPD_MIO_Sel (LPD_IOP_SLCR) Register Description
| Register Name | LPD_MIO_Sel |
|---|---|
| Relative Address | 0x0000000410 |
| Absolute Address | 0x00FF080410 (LPD_IOP_SLCR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x0003FFFF |
| Description | LPD IOP Routing Select to PMC or LPD MIO |
0: PMC MIO multiplexer 1: LPD MIO multiplexer Alternate register name: LPD_MIO_SEL
LPD_MIO_Sel (LPD_IOP_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:18 | razRead as zero | 0x0 | reserved |
| FPD_SWDT_SEL | 17 | rwNormal read/write | 0x1 | FPD system watchdog timer Note: Field name reference: WWDT1_SEL |
| LPD_SWDT_SEL | 16 | rwNormal read/write | 0x1 | LPD system watchdog timer Note: Field name reference: WWDT0_SEL |
| I2C1_SEL | 15 | rwNormal read/write | 0x1 | LPD I2C 1 interface |
| I2C0_SEL | 14 | rwNormal read/write | 0x1 | LPD I2C 0 interface |
| CAN1_SEL | 13 | rwNormal read/write | 0x1 | CAN 1 interface |
| CAN0_SEL | 12 | rwNormal read/write | 0x1 | CAN 0 interface |
| UART1_SEL | 11 | rwNormal read/write | 0x1 | UART 1 interface |
| UART0_SEL | 10 | rwNormal read/write | 0x1 | UART 0 interface |
| TTC3_SEL | 9 | rwNormal read/write | 0x1 | TTC 3 signals |
| TTC2_SEL | 8 | rwNormal read/write | 0x1 | TTC 2 signals |
| TTC1_SEL | 7 | rwNormal read/write | 0x1 | TTC 1 signals |
| TTC0_SEL | 6 | rwNormal read/write | 0x1 | TTC 0 signals |
| SPI1_SEL | 5 | rwNormal read/write | 0x1 | SPI 1 interface |
| SPI0_SEL | 4 | rwNormal read/write | 0x1 | SPI 0 interface |
| GEM1_MDIO_SEL | 3 | rwNormal read/write | 0x1 | GEM 1 MDIO interface |
| GEM1RGMII_SEL | 2 | rwNormal read/write | 0x1 | GEM 1 RGMII interface |
| GEM0_MDIO_SEL | 1 | rwNormal read/write | 0x1 | GEM 0 MDIO interface |
| GEM0RGMII_SEL | 0 | rwNormal read/write | 0x1 | GEM 0 RGMII interface |