DMA0_Route (PMC_INT_CSR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

DMA0_Route (PMC_INT_CSR) Register Description

Register NameDMA0_Route
Relative Address0x0000000018
Absolute Address 0x00F1330018 (PMC_INT_CSR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionRouting Register for DMA 0 AXI Transactions

Alternate register name: pmcdma0

DMA0_Route (PMC_INT_CSR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1rwNormal read/write0x0Select routing path:
0: Direct routing, no address translation or L2-cache coherency (SMMU, CCI)
1: Route transaction to the the SMMU TBU0 and cache coherent interconnect (CCI) in the FPD
routing 0rwNormal read/write0x0Select routing path:
0: Direct routing, no address translation or L2-cache coherency (SMMU, CCI)
1: Route transaction to the the SMMU TBU0 and cache coherent interconnect (CCI) in the FPD