PFx_PASID_CAP_MAX_PASID_WIDTH_12 (CPM5_PCIE_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)
Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PFx_PASID_CAP_MAX_PASID_WIDTH_12 (CPM5_PCIE_ATTR) Register Description

Register NamePFx_PASID_CAP_MAX_PASID_WIDTH_12
Relative Address0x0000002028
Absolute Address 0x00FCE0A028 (CPM5_PCIE0_ATTR)
0x00FCE8A028 (CPM5_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMax PASID Width. Permitted to be in the range 0D (single PASID) to 20D (all PASID value (20 bits))

This register should only be written to during reset of the PCIe block

PFx_PASID_CAP_MAX_PASID_WIDTH_12 (CPM5_PCIE_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 4:0rwNormal read/write0x0Max PASID Width. Permitted to be in the range 0D (single PASID) to 20D (all PASID value (20 bits))