PMEVCNTR11 (FPD_SMMU_TCU) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PMEVCNTR11 (FPD_SMMU_TCU) Register Description

Register NamePMEVCNTR11
Relative Address0x000000302C
Absolute Address 0x00FD80302C (FPD_SMMU_TCU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionProvides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.

PMEVCNTR11 (FPD_SMMU_TCU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PMN331:0rwNormal read/write0Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.