| Field Name | Bits | Type | Reset Value | Description |
|---|
| OIA | 3 | rwNormal read/write | 0x0 | Override idle Acknowledgment signal to processor. When it is 0: Processor waits for the debug register access logic to go idle before it enters the idle state. When it is 1, Processor does not wait for the debug register access logic to go idle before it enters the idle state. |
| CDRS | 2 | rwNormal read/write | 0 | Read-only status bit that reflects the current reset state of the debug logic in the processor power domain. 0: Debug logic in processor power domain is not in reset state. 1: Debug logic in processor power domain is currently in reset state |
| DPDO | 1 | rwNormal read/write | 0x0 | Debug powerdown control bit. If debug is enabled and this bit is 0: Error response is generated for APB accesses to the processor domain debug registers when the processor is powered down or OS Double Lock is set. If debug is enabled and this bit is 1: APB accesses to the processor domain debug registers proceed normally when the processor is powered down or OS Double Lock is set. |
| DCSC | 0 | rwNormal read/write | 0x0 | Debug clock control bit. If debug is enabled and this bit is 0: Does not prevent the clock generator from stopping the processor clock. If debug is enabled and this bit is 1: Prevents the clock generator from stopping the processor clock. |