PMC_PL_IRQ (PMC_GLOBAL) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PMC_PL_IRQ (PMC_GLOBAL) Register Description

Register NamePMC_PL_IRQ
Relative Address0x0000000930
Absolute Address 0x00F1110930 (PMC_GLOBAL)
Width32
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionPL Signal Interrupt Status

Four interrupt signals from the PL to the PPU. Reads: 0: interrupt not detected 1: interrupt detected (sticky, cleared by writing a 1) Status writes: 0: ignored 1: clears status bit to 0

PMC_PL_IRQ (PMC_GLOBAL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
IRQ_3 3wtcReadable, write a 1 to clear0x0Interrupt 3 from PL
IRQ_2 2wtcReadable, write a 1 to clear0x0Interrupt 2 from PL
IRQ_1 1wtcReadable, write a 1 to clear0x0Interrupt 1 from PL
IRQ_0 0wtcReadable, write a 1 to clear0x0Interrupt 0 from PL