DMA_DST_SIZE (OSPI) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

DMA_DST_SIZE (OSPI) Register Description

Register NameDMA_DST_SIZE
Relative Address0x0000001804
Absolute Address 0x00F1011804 (OSPI)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDestination DMA Payload Size

Alternate register name: OSPIDMA_DST_SIZE

DMA_DST_SIZE (OSPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:29razRead as zero0x0RESERVED. Return 0 when read. Writes ignored.
SIZE28:2rwNormal read/write0x0Specifies the number of 4-byte words the DMA will transfer from stream to memory
Size is word aligned, so this field is only 27-bits. (2 lsbs are 0)
The action of writing to this register starts a DMA transfer of length SIZE, moving data from the stream interface to ADDR. In this case, it indicates the total payload that the DMA will move from stream to memory.
After the DMA has started, this field will dynamically change under DMA control to reflect the remaining payload size that the DMA must still complete. Whenever a BRESP is returned from memory, the SIZE will decrement
by 1.
Reserved 1:0razRead as zero0x0RESERVED. Return 0 when read. Writes ignored.