ADV_SWTm_BAR3_CONTROL_1 (CPM5_PCIE_ATTR) Register Description
Register Name | ADV_SWTm_BAR3_CONTROL_1 |
---|---|
Relative Address | 0x000000234C |
Absolute Address |
0x00FCE0A34C (CPM5_PCIE0_ATTR) 0x00FCE8A34C (CPM5_PCIE1_ATTR) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | BAR3 Control - Specifies the configuration of BAR 3. For Endpoint, the various encodings are: 000: Disabled 001: 32-bit IO BAR 010-011: Reserved 100: 32-bit memory BAR, non-prefetchable 101: 32-bit memory BAR, prefetchable For non-Endpoint (Type 1) Config Space, the I/O Base & Limit encodings are: 000: Disabled 001: 16-bit I/O Enabled 011: 32-bit I/O Enabled 010,100-111: Reserved |
This register should only be written to during reset of the PCIe block
ADV_SWTm_BAR3_CONTROL_1 (CPM5_PCIE_ATTR) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
attr | 2:0 | rwNormal read/write | 0x0 | BAR3 Control - Specifies the configuration of BAR 3. For Endpoint, the various encodings are: 000: Disabled 001: 32-bit IO BAR 010-011: Reserved 100: 32-bit memory BAR, non-prefetchable 101: 32-bit memory BAR, prefetchable For non-Endpoint (Type 1) Config Space, the I/O Base & Limit encodings are: 000: Disabled 001: 16-bit I/O Enabled 011: 32-bit I/O Enabled 010,100-111: Reserved |