PL_SELF_TRAIN (CPM5_PCIE_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)
Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PL_SELF_TRAIN (CPM5_PCIE_ATTR) Register Description

Register NamePL_SELF_TRAIN
Relative Address0x0000000310
Absolute Address 0x00FCE08310 (CPM5_PCIE0_ATTR)
0x00FCE88310 (CPM5_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionEnabled Loopback Self Link Up when PL_UPSTREAM_FACING = FALSE. To be used by GOQ for Production Test.

This register should only be written to during reset of the PCIe block

PL_SELF_TRAIN (CPM5_PCIE_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 0rwNormal read/write0x0Enabled Loopback Self Link Up when PL_UPSTREAM_FACING = FALSE. To be used by GOQ for Production Test.