attr_dma_spare_2_h (CPM5_DMA_ATTR) Register Description
| Register Name | attr_dma_spare_2_h |
|---|---|
| Relative Address | 0x000000007C |
| Absolute Address |
0x00FCE1007C (CPM5_DMA0_ATTR) 0x00FCE9007C (CPM5_DMA1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | DMA configuration attributes Bits, Field, Recd Settings, Description [31], dis_c2h_avl_ring_process, If set, disable the C2H Avail Ring entry processing inside QDMA [30], fix_dbe_parity_dis, If set, disable fix for EDT-985612, generate invalid parity on dbe at write interfaces [29], pcie_rq_vf_flr_check_dis, If set, flr for vfs will be assumed to be false in dma_pcie_req [28], pcie_rq_pf_flr_check_dis, If set, flr for pfs will be assumed to be false in dma_pcie_req [27], mm_err_wbk_fix_dis, If set, disable the fix for the write completion from the DMA Write Engine [26], dis_c2h_ctxt_mgr_fix, If set, disable the C2H fix for ctxt mgr, affects both wrb and pfch [25], new_axiuser_en, If set, use new axiuser format [24], slv_bresp_fix_dis, If set, disable the fix for Slave Bresp (1: slv_wrq_commit; 0: slave_wcp_vld) [23], rcb128_en, If set, RCBs are 128B, if not set, RCBs are 64B [22], rcv_crd_chk_dis, If set, disable dsc engine received credit check [21], cfg_space_delay_en, If set, enable Bridge register to control config space enable in the EP mode [20:0], misc_cap, Misc capability registers, register accessible |
This register should only be written to during reset of the PCIe block
attr_dma_spare_2_h (CPM5_DMA_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 31:0 | rwNormal read/write | 0x0 | DMA configuration attributes Bits, Field, Recd Settings, Description [31], dis_c2h_avl_ring_process, If set, disable the C2H Avail Ring entry processing inside QDMA [30], fix_dbe_parity_dis, If set, disable fix for EDT-985612, generate invalid parity on dbe at write interfaces [29], pcie_rq_vf_flr_check_dis, If set, flr for vfs will be assumed to be false in dma_pcie_req [28], pcie_rq_pf_flr_check_dis, If set, flr for pfs will be assumed to be false in dma_pcie_req [27], mm_err_wbk_fix_dis, If set, disable the fix for the write completion from the DMA Write Engine [26], dis_c2h_ctxt_mgr_fix, If set, disable the C2H fix for ctxt mgr, affects both wrb and pfch [25], new_axiuser_en, If set, use new axiuser format [24], slv_bresp_fix_dis, If set, disable the fix for Slave Bresp (1: slv_wrq_commit; 0: slave_wcp_vld) [23], rcb128_en, If set, RCBs are 128B, if not set, RCBs are 64B [22], rcv_crd_chk_dis, If set, disable dsc engine received credit check [21], cfg_space_delay_en, If set, enable Bridge register to control config space enable in the EP mode [20:0], misc_cap, Misc capability registers, register accessible |