PS_MISC_IR_STATUS (CPM4_SLCR) Register Description
| Register Name | PS_MISC_IR_STATUS |
|---|---|
| Relative Address | 0x0000000340 |
| Absolute Address | 0x00FCA10340 (CPM4_SLCR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Interrupt Status Register for Miscellaneous CPM events. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
PS_MISC_IR_STATUS (CPM4_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:25 | roRead-only | 0x0 | Reserved |
| pl_irq1 | 24 | wtcReadable, write a 1 to clear | 0x0 | Status of interrupt 1 from PL |
| pl_irq0 | 23 | wtcReadable, write a 1 to clear | 0x0 | Status of interrupt 0 from PL |
| cpi1_err | 22 | wtcReadable, write a 1 to clear | 0x0 | Status of error interrupt from CPI 1 |
| cpi0_err | 21 | wtcReadable, write a 1 to clear | 0x0 | Status of error interrupt from CPI 0 |
| pcie1_ccix_pdvsec_cfg_wr_rcvd | 20 | wtcReadable, write a 1 to clear | 0x0 | Status of dvsec cfg write for pcie 1 |
| pcie1_ccix_pdvsec_cfg_rd_rcvd | 19 | wtcReadable, write a 1 to clear | 0x0 | Status of dvsec cfg read for pcie 1 |
| pcie0_ccix_pdvsec_cfg_wr_rcvd | 18 | wtcReadable, write a 1 to clear | 0x0 | Status of dvsec cfg write for pcie 0 |
| pcie0_ccix_pdvsec_cfg_rd_rcvd | 17 | wtcReadable, write a 1 to clear | 0x0 | Status of dvsec cfg read for pcie 0 |
| addrremap_err | 16 | wtcReadable, write a 1 to clear | 0x0 | Status of addresss translation error interrupt from addrremap block |
| l2_cache0_uncorr_err | 13 | wtcReadable, write a 1 to clear | 0x0 | Status of uncorrectable error from L2 cache 0 |
| l2_cache0_corr_err | 12 | wtcReadable, write a 1 to clear | 0x0 | Status of correctable error from L2 cache 0 |
| cmn_pmu_event | 11 | wtcReadable, write a 1 to clear | 0x0 | Status of performance counter overflow interrupt from CMN |
| cmn_faults | 10 | wtcReadable, write a 1 to clear | 0x0 | Status for secure fault interrupt from CMN |
| cmn_faultns | 9 | wtcReadable, write a 1 to clear | 0x0 | Status for non-secure fault interrupt from CMN |
| cmn_errs | 8 | wtcReadable, write a 1 to clear | 0x0 | Status for secure error interrupt from CMN |
| cmn_errns | 7 | wtcReadable, write a 1 to clear | 0x0 | Status for non-secure error interrupt from CMN |
| Reserved | 6 | roRead-only | 0x0 | Reserved |
| pcie1_cfg_msg_received | 5 | wtcReadable, write a 1 to clear | 0x0 | Status for cfg message received for pcie 1 |
| pcie0_cfg_msg_received | 4 | wtcReadable, write a 1 to clear | 0x0 | Status for cfg message received for pcie 0 |
| pcie_msi1 | 3 | wtcReadable, write a 1 to clear | 0x0 | Status for MSI received with vector 32-63 set, RP only. To decode this interrupt further, software must read XDMA_REG.MSI_DEC_63_32 register |
| pcie_msi0 | 2 | wtcReadable, write a 1 to clear | 0x0 | Status for MSI received with vector 0-31 set, RP only. To decode this interrupt further, software must read XDMA_REG.MSI_DEC_31_0 register |
| pcie_local_event | 1 | wtcReadable, write a 1 to clear | 0x0 | Status for PCIe local interrupt events and errors. To decode the reason for this interrupt, software must read XDMA_REG.INT_DEC register. |
| apb_err | 0 | wtcReadable, write a 1 to clear | 0x0 | Status for an APB error interrupt. To decode this interrupt further, software must read the following registers: CPM_CRCPM.IR_STATUS PCIEA_ATTRIB_0.ISR PCIEA_ATTRIB_1.ISR PCIEA_ATTRIB_DMA.ISR INTCPM_CONFIG.IR_STATUS CPM_SLCR_SECURE.IR_STATUS CPM_ADDRREMAP.IR_STATUS CPM_SLCR.IR_STATUS |