PFx_SRIOV_CAP_TOTAL_VF_1 (CPM5_PCIE_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PFx_SRIOV_CAP_TOTAL_VF_1 (CPM5_PCIE_ATTR) Register Description

Register NamePFx_SRIOV_CAP_TOTAL_VF_1
Relative Address0x000000160C
Absolute Address 0x00FCE0960C (CPM5_PCIE0_ATTR)
0x00FCE8960C (CPM5_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionTotal Number of VFs: Total number of VFs configured for PF0. Must be equal to PF0_SRIOV_CAP_INITIAL_VF. Count must be power of 2 for PF0_SRIOV_VF_STRIDE > 1.

This register should only be written to during reset of the PCIe block

PFx_SRIOV_CAP_TOTAL_VF_1 (CPM5_PCIE_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr15:0rwNormal read/write0x0Total Number of VFs: Total number of VFs configured for PF0. Must be equal to PF0_SRIOV_CAP_INITIAL_VF. Count must be power of 2 for PF0_SRIOV_VF_STRIDE > 1.