intxram_bank0_apb_power_main_ResilienceFaultController_BistCtl (XRAM_INT_GPV) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

intxram_bank0_apb_power_main_ResilienceFaultController_BistCtl (XRAM_INT_GPV) Register Description

Register Nameintxram_bank0_apb_power_main_ResilienceFaultController_BistCtl
Relative Address0x0000000534
Absolute Address 0x00FF940534 (XRAM_INT_GPV)
Width32
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionBistControl register

intxram_bank0_apb_power_main_ResilienceFaultController_BistCtl (XRAM_INT_GPV) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
BISTDONECLR 1wtcReadable, write a 1 to clear0x0Clear BistDone
BISTSTART 0wtcReadable, write a 1 to clear0x0Start Bist sequence