IDR0 (PMC_SYSMON_CSR) Register Description
| Register Name | IDR0 |
|---|
| Relative Address | 0x0000000050 |
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| Absolute Address |
0x00F1270050 (PMC_SYSMON_CSR)
|
|---|
| Width | 32 |
|---|
| Type | woWrite-only |
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| Reset Value | 0x00000000 |
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| Description | Disable for Interrupt Signal 0 |
|---|
Interrupt Signal 0 Disable Bits (write-only): 0: no effect 1: sets the mask bit = 1 (disables the interrupt signal) Note: Refer to the ISR register for more information. Alternate register name: REG_IDR0
IDR0 (PMC_SYSMON_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| NEW_DATA3 | 15 | woWrite-only | 0x0 | New Data Detected Reg 3 |
| NEW_DATA2 | 14 | woWrite-only | 0x0 | New Data Detected Reg 2 |
| NEW_DATA1 | 13 | woWrite-only | 0x0 | New Data Detected Reg 1 |
| NEW_DATA0 | 12 | woWrite-only | 0x0 | New Data Detected Reg 0 |
| TEMP | 9 | woWrite-only | 0x0 | Device-Temperature Limit |
| OT | 8 | woWrite-only | 0x0 | Over-Temperature Limit |
| ALARM7 | 7 | woWrite-only | 0x0 | Alarm 7 |
| ALARM6 | 6 | woWrite-only | 0x0 | Alarm 6 |
| ALARM5 | 5 | woWrite-only | 0x0 | Alarm 5 |
| ALARM4 | 4 | woWrite-only | 0x0 | Alarm 4 |
| ALARM3 | 3 | woWrite-only | 0x0 | Alarm 3 |
| ALARM2 | 2 | woWrite-only | 0x0 | Alarm 2 |
| ALARM1 | 1 | woWrite-only | 0x0 | Alarm 1 |
| ALARM0 | 0 | woWrite-only | 0x0 | Alarm 0 |