MIO_PIN_24 (PMC_IOP_SLCR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

MIO_PIN_24 (PMC_IOP_SLCR) Register Description

Register NameMIO_PIN_24
Relative Address0x0000000060
Absolute Address 0x00F1060060 (PMC_IOP_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionPMC MIO Pin 24 Configuration

MIO_PIN_24 (PMC_IOP_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:10razRead as zero0x0reserved
L3_SEL 9:7rwNormal read/write0x0Level 3 Mux Select
0: SYSMON_I2C_SDA input/output
1: reserved
2: reserved
3: reserved
4: reserved
5: reserved
6: reserved
7: PCIe_RESET1_b input
L2_SEL 6:5rwNormal read/write0x0Level 2 Mux Select
0: Level 3 Mux
1: reserved
2: reserved
3: PMC_GPIO[24] input/output
L1_SEL 4:3rwNormal read/write0x0Level 1 Mux Select
0: Level 2 Mux
1: reserved
2: reserved
3: reserved
L0_SEL 2:1rwNormal read/write0x0Level 0 Mux Select
0: Level 1 Mux
1: SD0_DETECT input
2: SMAP_IO[6] input/output
3: USB_ULPI_STP output
Reserved 0razRead as zero0x0reserved