cpm_ps_axi0_wr_I_main_QosGenerator_Bandwidth (LPD_INT_GPV) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

cpm_ps_axi0_wr_I_main_QosGenerator_Bandwidth (LPD_INT_GPV) Register Description

Register Namecpm_ps_axi0_wr_I_main_QosGenerator_Bandwidth
Relative Address0x0000000290
Absolute Address 0x00FE400290 (LPD_INT_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000A00
Descriptioncpm_ps_axi0_wr_I_main_QosGenerator_Bandwidth

Alternate register name: if_cpm_ps_axi0_wr_I_main_QosGenerator_Bandwidth

cpm_ps_axi0_wr_I_main_QosGenerator_Bandwidth (LPD_INT_GPV) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
BANDWIDTH12:0rwNormal read/write0xA00Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words, the desired rate in MBps is divided by frequency in MHz of the NIU, and then multiplied by 256.