IMR (XPPU) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

IMR (XPPU) Register Description

Register NameIMR
Relative Address0x0000000014
Absolute Address 0x00FF990014 (LPD_XPPU)
0x00F1310014 (PMC_XPPU)
0x00F1300014 (PMC_XPPU_NPI)
Width32
TyperoRead-only
Reset Value0x000000EF
DescriptionAccess Violations Interrupt Mask

0: enabled. 1: masked (disabled). Note: If the ISR bit = 1 (asserted interrupt) and the IMR bit = 0 (not masked), then the system IRQ to the interrupt controller is asserted. Software checks the ISR to determine the cause of the interrupt. Read-only.

IMR (XPPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8roRead-only0x0reserved
APER_PARITY 7roRead-only0x1Parity Error mask status
APER_TZ 6roRead-only0x1TrustZone Violation mask status.
APER_PERM 5roRead-only0x1Access Violation mask status.
Reserved 4roRead-only0x0reserved
SMID_PARITY 3roRead-only0x1SMID Parity Error mask status.
Note: Field name reference: MID_PARITY
SMID_RO 2roRead-only0x1Read permission Violation mask status.
Note: Field name reference: MID_RO
SMID_MISS 1roRead-only0x1System management (SMID) Not Found mask status.
Note: Field name reference: MID_MISS
INV_APB 0roRead-only0x1Register Access Error on APB mask status.