CCIX_CFG_MGMT_MUX_ENABLE (CPM4_PCIE0_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)
Document ID
AM012
Release Date
2023-08-29
Revision
1.3

CCIX_CFG_MGMT_MUX_ENABLE (CPM4_PCIE0_ATTR) Register Description

Register NameCCIX_CFG_MGMT_MUX_ENABLE
Relative Address0x0000000A2C
Absolute Address 0x00FCA50A2C (CPM4_PCIE0_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionCCIX Cfg Management Mux Enable: In PCIe Block A, when TRUE enables Cfg Management Mux. When FALSE disables Cfg Management Mux (bypass mode).

This register should only be written to during reset of the PCIe block

CCIX_CFG_MGMT_MUX_ENABLE (CPM4_PCIE0_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 0rwNormal read/write0x0CCIX Cfg Management Mux Enable: In PCIe Block A, when TRUE enables Cfg Management Mux. When FALSE disables Cfg Management Mux (bypass mode).