PFx_PRI_STATUS_PRG_RESP_PASID_REQD_7 (CPM5_PCIE_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)
Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PFx_PRI_STATUS_PRG_RESP_PASID_REQD_7 (CPM5_PCIE_ATTR) Register Description

Register NamePFx_PRI_STATUS_PRG_RESP_PASID_REQD_7
Relative Address0x0000001DA8
Absolute Address 0x00FCE09DA8 (CPM5_PCIE0_ATTR)
0x00FCE89DA8 (CPM5_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPRI PRG RESP PASID REQD Status

This register should only be written to during reset of the PCIe block

PFx_PRI_STATUS_PRG_RESP_PASID_REQD_7 (CPM5_PCIE_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 0rwNormal read/write0x0PRI PRG RESP PASID REQD Status