TRCACATRL3 (DBG_A720_ETM) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

TRCACATRL3 (DBG_A720_ETM) Register Description

Register NameTRCACATRL3
Relative Address0x0000000498
Absolute Address 0x00F0D30498 (DBG_APU0_ETM)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionAddress Comparator Access Type Register 3

TRCACATRL3 (DBG_A720_ETM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
EXLEVEL_NS15:12rwNormal read/write0x0In Non-secure state, each bit controls whether a comparison can occur for the corresponding exception level:The exception levels are:Bit[12]Exception level 0. Bit[13]Exception level 1.Bit[14]Exception level 2.Bit[15]RAZ/WI. EXLEVEL_NS[3] is never implemented.The content of the field is IMPLEMENTATION DEFINED and is set by the value of IDR3.EXLEVEL_NS. Unimplemented bits are RAZ/WI.
EXLEVEL_S11:8rwNormal read/write0x0In Secure state, each bit controls whether a comparison can occur for the corresponding exception level:The exception levels are:Bit[8]Exception level 0. Bit[9]Exception level 1.Bit[10]RAZ/WI. EXLEVEL_S[2] is never implemented.Bit[11]Exception level 3.The content of the field is IMPLEMENTATION DEFINED and is set by the value of IDR3.EXLEVEL_S. Unimplemented bits are RAZ/WI.
Context_type 3:2rwNormal read/write0If IDR4. NUMVMIDC>0 and IDR4.NUMCIDC>0, this field controls whether the trace unit performs a Context ID comparison, a virtual machine identifier (VMID) comparison, or both comparisons:If IDR4.NUMVMIDC==0 and IDR4.NUMCIDC>0, bit [3] is RES0 and bit[2] controls whether the trace unit performs a Context ID comparison, as with cases 0b00 and 0b01 above.If IDR4.NUMVMIDC==0 and IDR4.NUMCIDC==0, both bits are RES0.
Type 1:0roRead-only0x0Controls what type of comparison the trace unit performs:If IDR4. SUPPDAC does not indicate that data address comparisons are implemented, then this field is RES0. This means that any comparison performed by this address comparator is an instruction address comparison.