SMMU_CB12_TCR2 (FPD_SMMU_TCU) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID: AM012
Release Date: 2023-08-29
Revision: 1.3

SMMU_CB12_TCR2 (FPD_SMMU_TCU) Register Description

Register Name	SMMU_CB12_TCR2
Relative Address	0x000002C010
Absolute Address	0x00FD82C010 (FPD_SMMU_TCU)
Width	32
Type	mixedMixed types. See bit-field details.
Reset Value	0x00000060
Description	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.

SMMU_CB12_TCR2 (FPD_SMMU_TCU) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
NSCFG1	30	rwNormal read/write	0	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SEP	17:15	rwNormal read/write	0	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
NSCFG0	14	rwNormal read/write	0	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
TBI1	6	roRead-only	0x1	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
TBI0	5	roRead-only	0x1	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
AS	4	rwNormal read/write	0	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
PASize	2:0	rwNormal read/write	0	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.