SMMU_CB8_TTBR0_low (FPD_SMMU_TCU) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID: AM012
Release Date: 2023-08-29
Revision: 1.3

SMMU_CB8_TTBR0_low (FPD_SMMU_TCU) Register Description

Register Name	SMMU_CB8_TTBR0_low
Relative Address	0x0000028020
Absolute Address	0x00FD828020 (FPD_SMMU_TCU)
Width	32
Type	mixedMixed types. See bit-field details.
Reset Value	0x00000000
Description	The Translation Table Base register 0 holds the base address of the translation table 0.

SMMU_CB8_TTBR0_low (FPD_SMMU_TCU) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
ADDRESS_31_7	31:7	rwNormal read/write	0	The Translation Table Base register 0 holds the base address of the translation table 0.
ADDRESS_6_IRGN0	6	rwNormal read/write	0	The Translation Table Base register 0 holds the base address of the translation table 0.
ADDRESS_5_NOS	5	rwNormal read/write	0	The Translation Table Base register 0 holds the base address of the translation table 0.
ADDRESS_4_3_RGN	4:3	rwNormal read/write	0	The Translation Table Base register 0 holds the base address of the translation table 0.
ADDRESS_2	2	roRead-only	0x0	The Translation Table Base register 0 holds the base address of the translation table 0.
ADDRESS_1_S	1	rwNormal read/write	0	The Translation Table Base register 0 holds the base address of the translation table 0.
ADDRESS_0_IRGN1	0	rwNormal read/write	0	The Translation Table Base register 0 holds the base address of the translation table 0.