Interconnect
The NoC interconnect and NPI programming interface are new in the Versal adaptive SoC and significantly affect the overall architecture of the device by giving all parts of the device direct access to one or more memory controllers and all of the integrated blocks in the device.
The Versal adaptive SoC adds a unifying NPI programming interface for all the non-PMC and PS register modules that use the APB interface with single word reads and writes. The NPI host controller is located on the PMC main interconnect switch and can burst program the register memory space.
The Versal device's main and IOP interconnect switches within the PMC and PS have similar hardware architectures as the Zynq UltraScale+ MPSoCs, but with very different implementations for timeout and isolation. The Versal device interconnects include parity generation and checking and greater control over TrustZone security and transaction routing.
AXI Timeout Comparisons
The AXI timeout function in the Versal adaptive SoC is implemented on the ePorts of the interconnect with new IP. The timeout function is similar to the Zynq UltraScale+ MPSoC but the instances and programming model are different.
AXI and APB Isolation Comparisons
Isolation is done at the ports of the interconnect instead of using individual AXI isolation blocks (AIB). Both the iPorts and ePorts include isolation.
CCI QVN Support
The cache coherent interface (CCI-400) in the Zynq UltraScale+ MPSoC supports QVN. However, the CCI-500 in the Versal device does not include support for QVN.