Functionality
- Boundary-scan
- Basic TAP controller register access
- Extended TAP controller register access
- Secondary TAP controller register access in SSI technology devices
- CoreSight™ DAP controller register access
- CoreSight processor and system debug hardware
- Debug packet controller (DPC)
- Peripherals with loopback hardware
Architecture
- JTAG interface
- JTAG chain architecture for monolithic and SSI technology devices
- TAP controller
- Arm® DAP controller
- DPC subsystem
SoC Debug I/O
The AMD Versal™ adaptive SoC includes device-level debug and trace capabilities. The debug hardware features include the following.
- Four host debugger access points to the DPC:
- PCIe® Host: high-speed, high-bandwidth debug protocol
- Aurora host: high-speed, serial debug protocol path to DPC
- PL interface: high-speed, high-bandwidth streaming
- JTAG
- Debug environment for the following:
- PS RPU and APU processors
- PMC and PSM processors
- PL, CPM, and AI Engine
- Intrusive and non-intrusive debug
- Interfacing to ChipScope™
- Daisy-chaining of multiple devices for debug or configuration through a unified cable