The persistent clock and reset registers are summarized in the following table.
Register | Offset Address | Description |
---|---|---|
PMC CRP Clock and Reset Register Module | ||
|
Software boot mode control and status. |
|
|
Resets: [PMC_POR], [PS_POR], [PL_POR] only. Non-PS, PMC resets: [SOC_POR] only. Reset for Debug blocks. | |
LPD CRL Clock and Reset Register Module | ||
|
RPU |
|
FPD CRF Clock and Reset Register Module | ||
|
APUCortex-A72 hard resets: [APUx_PWRON]. |