The programming interface is connected to the LPD APB switch by default. In devices that support the PL interface, this interface can be switched to a PL AXI interface by setting the xxxxxx bit in the xxxxx register.
- LPD APB Interface
- The registers are accessible from the LPD APB switch:
- XRAM_SLCR status and control register set at 0xFF95_0000
- XRAM_INT_GPV crossbar control register set at 0xFF94_0000
- XRAM_XMPU[0:3] memory protection register sets (x4) at 0xFF93_0000, 0xFF93_4000, 0xFF93_8000, 0xFF93_C000
- XRAM_CTRL[0:3] memory bank control register sets (x4) at 0xFF8E_0000, 0xFF8F_0000, 0xFF90_0000, 0xFF91_0000
- PL AXI Interface
- The PL programming interface is based on a 32-bit AXI protocol.
Figure 1.
Control and
Status Access Block Diagram
Note: Only certain devices
support the PL interfaces. See Devices with Accelerator RAM and Access Ports.