Boot Mode Implementations

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The boot interfaces are divided into autonomous and supervised. The autonomous modes require a simple flash memory interface. The supervisor boot modes require an external controller connected to the JTAG or SMAP interface.

Autonomous Boot Interface Implementations

The following table summarizes the implementations for the flash boot interfaces.

Table 1. Autonomous Boot Interface Implementations
Device Generation OSPI QSPI SD eMMC NAND
UltraScale+ MPSoC Not available 24-bit, 32-bit addressing v2.0/3.0 via SD_eMMC combination controller v4.51 via SD_eMMC combination controller 8-bit ONFI v3.1 (512 Gb)
Versal device 8-bit data

1-bit, 2-bit, 4-bit (single or dual-stacked), or

8-bit (dual-parallel)

v2.0/3.0 via SD_eMMC combination controller v4.51 via SD_eMMC combination controller Not available 1
  1. Octal SPI and eMMC1 modes supersede the BPI and NAND modes used in previous architectures. Octal SPI and eMMC1 modes provide similar performance while reducing pin count.

Supervised Boot Interface Implementations

Table 2. Supervised Boot Interface Implementations
Device Generation USB JTAG SelectMap
UltraScale+ MPSoC v2.0 PS JTAG and PL JTAG controller interfaces Not available
Versal device USB boot not available PMC JTAG controller interface 8-bit, 16-bit, and 32-bit with SMAP Busy monitoring 1
  1. SelectMAP mode supports PDI loading only and requires hardware flow control using a BUSY signal.

The Versal device's new PMC centralized integration provides support for basic boot and configuration, Dynamic Function eXchange (DFX), power management, and reliability and safety functions from a single controller. The PMC bus architecture enables significantly faster configuration when compared with previous architectures. The following table summarizes the boot mode differences between architectures.

Table 3. Boot Mode Comparison
Mode Virtex UltraScale+ or Kintex UltraScale+ FPGA Zynq UltraScale+ MPSoC or Zynq UltraScale+ RFSoC Versal Adaptive SoC
JTAG Yes Yes Yes
OSPI Yes
QSPI32

Yes

Yes

Yes

QSPI24

Yes

Yes

Yes

SelectMAP Yes Yes 1
eMMC1 (4.51) Yes Yes
SD1 (3.0) Yes Yes
SD1 (2.0) Yes Yes
SD0 (3.0) Yes
SD0 (2.0) Yes
PJTAG_0
PJTAG_1 Yes
Serial Yes
BPI Yes Note 2
NAND Yes Note 2
USB (2.0) Yes
  1. Versal SelectMAP mode supports PDI loading only and requires hardware flow control using a BUSY signal.
  2. Octal SPI and eMMC1 modes supersede the BPI and NAND modes used in previous architectures. Octal SPI and eMMC1 modes provide similar performance while reducing pin count.