The DST DMA module receives data from the stream switch and writes it to the AXI4 interface. General AXI4 transaction characteristics include:
- AWSIZE is always
100b, indicating 128-bit data width. - The default AWLEN =
1111b, indicating 16 beats of data. The first and last command can have any AWLEN value. - AWPROT[1] is always = 0, indicating a secure command.
- AWCACHE[1] is always = 1, indicating upsizing is allowed.
- AWID is not used by the DST DMA module because the thread is single.
- AWBURST defaults to
01b, indicating an INCR burst. There is a register option to change the burst type to FIXED (AWBURST =00b).
The DMA write transfer begins when the PMC_DMA_DST_SIZE register location is written with a non-zero value.
The address must align to 16 byes and the size must be a multiple of 16 bytes.