Message Transmission

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

All messages written in the TX buffer should follow the required message format for ID, DLC, and DW fields described earlier. Each [RRnn] bit in the TxBuff_Ready_Req register corresponds to a message element in the TX buffer.

Software Actions

  1. Poll the TxBuff_Ready_Req register to check current pending transmission requests.
  2. If all of the register bits are set, a new transmission request can be added only if:
    1. One or more buffer transmission requests are canceled, or
    2. One or more buffer transmission completes
  3. If one or more bits of the TxBuff_Ready_Req register are unset/clear, a new transmission request can be added as follows:
    1. Prepare one or more message elements in the TX buffers (by writing valid ID, DLC, and DW fields of each message element of the respective TX buffer). If event logging is required for this message element, set the [EFC] bit in one of the TxBuff_DLC_Msg_n registers.
    2. Enable interrupt generation as required.
    3. Set corresponding TxBuff_Ready_Req register bits to enable buffer ready requests. The host can enable many transmission requests in one register write.
    4. Wait for interrupt (if enabled) or poll the TxBuff_Ready_Req register to gather the request status.
  4. The controller clears the TxBuff_Ready_Req register bit when a respective buffer request is completed (either due to transmission, cancellation, or DAR mode transmission).
  5. The host can read the TX event buffer to determine the message timestamps and the order of transmissions.
    Note: The APB_MISC_ISR [TXOK] bit is set after the core successfully transmits a message. The APB_MISC_ISR [ARBLST] bit is set if the controller loses bus arbitration while transmitting a message. The [ERROR] bit in the Intr_Status register is set if the message transmission encountered any errors.

Controller Actions

  1. The controller determines the next highest priority buffer to be transmitted. If two buffers have the same ID, the buffer with the lower index is selected.
  2. If enabled, copies the ID and DLC fields to the TX event buffer and adds a message timestamp and event type.
  3. Clears the respective bit in the TxBuff_Ready_Req register when the transmission request is served (either by successful transmission on the CAN bus, cancellation, or DAR-based transmission).
  4. If enabled through the TxBuff_Ready_Req_Intr_En (IETRS) or APB_MISC_IER (IER) registers, then the APB_MISC_ISR [TXRRS] bit is set = 1 and an interrupt is generated.
Note: The controller accesses the message element space of a buffer in the TX buffer only if the respective bit in the TxBuff_Ready_Req register is set.
Note: The software should respect the access rule to avoid memory collisions. That is, after the software sets a buffer ready request through the TxBuff_Ready_Req register, the software should not read or write the respective message element space until the respective [RRnn] bit is in a clear/unset state.
Note: The controller updates TX event FIFO status after clearing the respective bit. It is recommended either to use the TX event FIFO watermark full interrupt or poll TX Event FIFO status register to process the TX events.

TX events status may be useful for software to determine the order of TX buffers and get the transmission timestamp for buffers. This is provided through a separate pipe (TX Event FIFO) so it is de-linked with the individual buffer transmission in the TxBuff_Ready_Req . This separate FIFO should allow software to do this post-processing in batches; asynchronously with respect to individual buffer transmission.