LPD Interconnect Diagram

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The PS low-power domain (LPD) includes the Cortex-R5F MPCore processors with their tightly-coupled memories (TCM), OCM memory, and the PSM controller for PS power control. The RPU also has a direct interconnect to the accelerator RAM (XRAM, if present) that can be partitioned and shared with logic in the PL. The PS LPD interconnect includes the RPU MPCore, OCM, PSM controller, and the I/O peripherals (IOP). The LPD has several connections to I/O pins.

The following figure shows a block diagram of the LPD.

Figure 1. PS LPD Interconnect Diagram
Note: For details on the interconnect channels and ports, see the figures in the LPD and OCM Interconnect and LPD IOP Interconnect sections.