The following table describes the Arm Cortex-R5F processor implementation. These are fixed in hardware.
Note: For more information, see
the
Arm
Cortex-R5F Technical Reference
Manual.
| Configuration Parameter | Value | Description |
|---|---|---|
| INITPPX | 1 | AXI peripheral interface enabled at reset |
| SLBTCMSB | 0 | B0 and B1 TCM interleaving by addr [3] |
| INITRAMA | 0 | Enable TCM_A |
| INITRAMB | 1 | Enable TCM_B |
| ENTCM1IF | 1 | Enable TCM_B1 interface |
| LOCZRAMA | 1 | TCM_A initial base address is zero |
| PPXBASE | Global | Base address of AXI peripheral interface |
| PPXSIZE | 16 MBs | Size of AXI peripheral interface |
| PPVBASE | Global | Base address of virtual-AXI peripheral interface |
| PPVSIZE | 8 KBs | Size of virtual-AXI peripheral interface |