Cache Coherent Interconnect

Versal Adaptive SoC Technical Reference Manual (AM011)

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The cache coherent interconnect (CCI) is a coherent interconnect that enables hardware coherency. In hardware coherent systems, an operating system can run over multiple processor clusters without complicated cache maintenance software.

The CCI provides tight memory coherency between the APU L2 cache and a PL system cache using the ACE interface protocol to support multiple heterogeneous processing environments. The CCI is part of the FPD interconnect. It is based on the Arm® CCI-500 with its snoop filter (SF) table feature.

The hardware-based I/O coherency is used by transaction hosts using the ACE-Lite interface protocol. The ACE-Lite ingress ports attach to the LPD, CPM, NoC, and PL. The address of the transaction requests are compared with previously cached memory in the APU L2 cache and a PL system cache, if it is instantiated and connected.

The CCI can issue a snoop request to the ACE interfaces and use its snoop filter table to determine if a memory location is cached. If there is a cache hit, the data is returned to the source. When the transaction is non-cacheable or the memory address of the transaction is not in a cache (miss), the CCI operates like a regular interconnect and forwards the transaction to the memory address destination.

There are two register modules dedicated to the CCI. These include the FPD_CCI_CORE register module based on the IP from Arm, the much smaller FPD_CCI_CSR register module, and three registers in the LPD_SLCR register module for controlling stripping of the output ports to the NoC interconnect. These are listed in the CCI Register Reference section.

ACE Ports

The ACE ports tie the APU and PL processing complexes together so they can have a cache coherent shared memory space.

  • APU MPCore with L2-cache
  • PL MicroBlazeâ„¢ with system cache

ACE-Lite Ports

The ACE-Lite ingress ports provide I/O coherency for transactions for host transactions from several sources.

  • LPD-routed transactions, TBU0
  • NoC transactions, TBU1
  • PL and NoC transactions, TBU2
  • CPM transactions, TBU3

The AxCACHE signals provide caching and buffering information. See AxCACHE.

CCI Destination AXI Interfaces

There are six AXI interfaces routed to the following destinations.

  • FPD switch, AXI 0
  • FPD CPM switch, AXI 1
  • NoC 0, AXI 2
  • NoC 1, AXI 3
  • NoC 2, AXI 4
  • NoC 3, AXI 5

CCI Snoop Filter Table

The CCI-500 includes a snoop filter that provides an efficient way to determine if an address is cached. The snoop filter can often resolve coherency messaging without broadcasting a snoop request to both ACE interfaces.

ACP Interface to APU MPCore

A PL processor without a system cache can attach directly to the APU MPCore snoop control unit (SCU) using the ACP interface (PL_ACP_FPD). This enables the PL processor memory accesses to be coherent with the APU caches.
Note: The PL_ACP_FPD interface does not go to the CCI; it is included here as an alternative to using the CCI. The PL_ACP_FPD interface is described in the ACP Interface section.